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audio-synth/dev/general/MainSys/Project Logs for MainSys/TOP SCH ECO 26.12.2025 22-47-14.LOG
Erik Tóth c661422a10 PCB WIP 2 
All routing done, ready for review regarding the schematics, still have to do some silk screens...
2025-12-27 01:02:47 +01:00

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Change Component Designator: Old Designator=D? New Designator=D1
Change Component Designator: Old Designator=D? New Designator=D2
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