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f0b0b62eaa9d7dd698af203a52c7a3f573cdb360
audio-synth/dev/general/MainSys/History
History
Erik Tóth f0b0b62eaa PCB done 
Ready for order; waiting for check
2025-12-28 22:38:23 +01:00
..
CV_GEN.~(1).SchDoc.Zip
Main schematic update
2025-12-11 20:43:15 +01:00
CV_GEN.~(6).SchDoc.Zip
Further additions general schematics
2025-12-13 11:36:54 +01:00
CV_GEN.~(7).SchDoc.Zip
Further additions general schematics
2025-12-13 11:36:54 +01:00
CV_GEN.~(8).SchDoc.Zip
Started PCB Design
2025-12-24 23:04:43 +01:00
CV_GEN.~(9).SchDoc.Zip
PCB WIP 2
2025-12-27 01:02:47 +01:00
CV_GEN.~(10).SchDoc.Zip
PCB WIP 2
2025-12-27 01:02:47 +01:00
CV_GEN.~(11).SchDoc.Zip
PCB WIP 2
2025-12-27 01:02:47 +01:00
EXT.~(1).SchDoc.Zip
Main schematic update
2025-12-11 20:43:15 +01:00
EXT.~(2).SchDoc.Zip
Main schematic update
2025-12-11 20:43:15 +01:00
EXT.~(3).SchDoc.Zip
Main schematic update
2025-12-11 20:43:15 +01:00
EXT.~(4).SchDoc.Zip
Harness for SC1 and SC2 added
2025-12-11 22:58:54 +01:00
EXT.~(5).SchDoc.Zip
Harness for SC1 and SC2 added
2025-12-11 22:58:54 +01:00
EXT.~(6).SchDoc.Zip
Further additions general schematics
2025-12-13 11:36:54 +01:00
EXT.~(7).SchDoc.Zip
Further additions general schematics
2025-12-13 11:36:54 +01:00
EXT.~(8).SchDoc.Zip
Further additions general schematics
2025-12-13 11:36:54 +01:00
EXT.~(9).SchDoc.Zip
Further additions general schematics
2025-12-13 11:36:54 +01:00
EXT.~(18).SchDoc.Zip
Further additions general schematics
2025-12-13 11:36:54 +01:00
EXT.~(19).SchDoc.Zip
Further additions general schematics
2025-12-13 11:36:54 +01:00
EXT.~(20).SchDoc.Zip
Further additions general schematics
2025-12-13 11:36:54 +01:00
EXT.~(21).SchDoc.Zip
Further additions general schematics
2025-12-13 11:36:54 +01:00
EXT.~(22).SchDoc.Zip
Further additions general schematics
2025-12-13 11:36:54 +01:00
EXT.~(23).SchDoc.Zip
Further additions general schematics
2025-12-13 11:36:54 +01:00
EXT.~(24).SchDoc.Zip
Further additions general schematics
2025-12-13 11:36:54 +01:00
EXT.~(25).SchDoc.Zip
Further additions general schematics
2025-12-13 11:36:54 +01:00
EXT.~(26).SchDoc.Zip
Main schematic progress; checked VCA -> Voice Mixer compatibilty; DA Lib Update to V3.2
2025-12-14 16:41:19 +01:00
EXT.~(27).SchDoc.Zip
PCB main schematic progress
2025-12-18 16:28:24 +01:00
EXT.~(28).SchDoc.Zip
PCB main schematic progress
2025-12-18 16:28:24 +01:00
EXT.~(29).SchDoc.Zip
PCB main schematic progress
2025-12-18 16:28:24 +01:00
EXT.~(30).SchDoc.Zip
Started PCB Design
2025-12-24 23:04:43 +01:00
EXT.~(31).SchDoc.Zip
Started PCB Design
2025-12-24 23:04:43 +01:00
EXT.~(32).SchDoc.Zip
Started PCB Design
2025-12-24 23:04:43 +01:00
EXT.~(33).SchDoc.Zip
Started PCB Design
2025-12-24 23:04:43 +01:00
EXT.~(34).SchDoc.Zip
PCB WIP 2
2025-12-27 01:02:47 +01:00
EXT.~(35).SchDoc.Zip
PCB WIP 2
2025-12-27 01:02:47 +01:00
EXT.~(36).SchDoc.Zip
PCB WIP 2
2025-12-27 01:02:47 +01:00
EXT.~(37).SchDoc.Zip
PCB WIP 2
2025-12-27 01:02:47 +01:00
MAIN.~(1).PcbDoc.Zip
Started PCB Design
2025-12-24 23:04:43 +01:00
MAIN.~(2).PcbDoc.Zip
Started PCB Design
2025-12-24 23:04:43 +01:00
MAIN.~(3).PcbDoc.Zip
Started PCB Design
2025-12-24 23:04:43 +01:00
MAIN.~(4).PcbDoc.Zip
Started PCB Design
2025-12-24 23:04:43 +01:00
MAIN.~(5).PcbDoc.Zip
Started PCB Design
2025-12-24 23:04:43 +01:00
MAIN.~(6).PcbDoc.Zip
Started PCB Design
2025-12-24 23:04:43 +01:00
MAIN.~(7).PcbDoc.Zip
Started PCB Design
2025-12-24 23:04:43 +01:00
MAIN.~(8).PcbDoc.Zip
Started PCB Design
2025-12-24 23:04:43 +01:00
MAIN.~(9).PcbDoc.Zip
Started PCB Design
2025-12-24 23:04:43 +01:00
MAIN.~(10).PcbDoc.Zip
PCB WIP
2025-12-26 00:42:46 +01:00
MAIN.~(11).PcbDoc.Zip
PCB WIP
2025-12-26 00:42:46 +01:00
MAIN.~(12).PcbDoc.Zip
PCB WIP
2025-12-26 00:42:46 +01:00
MAIN.~(13).PcbDoc.Zip
PCB WIP
2025-12-26 00:42:46 +01:00
MAIN.~(14).PcbDoc.Zip
PCB WIP
2025-12-26 00:42:46 +01:00
MAIN.~(15).PcbDoc.Zip
PCB WIP 2
2025-12-27 01:02:47 +01:00
MAIN.~(16).PcbDoc.Zip
PCB WIP 2
2025-12-27 01:02:47 +01:00
MAIN.~(17).PcbDoc.Zip
PCB WIP 2
2025-12-27 01:02:47 +01:00
MAIN.~(18).PcbDoc.Zip
PCB WIP 2
2025-12-27 01:02:47 +01:00
MAIN.~(19).PcbDoc.Zip
PCB WIP 2
2025-12-27 01:02:47 +01:00
MAIN.~(20).PcbDoc.Zip
PCB WIP 2
2025-12-27 01:02:47 +01:00
MAIN.~(21).PcbDoc.Zip
PCB WIP 2
2025-12-27 01:02:47 +01:00
MAIN.~(22).PcbDoc.Zip
PCB WIP 2
2025-12-27 01:02:47 +01:00
MAIN.~(23).PcbDoc.Zip
PCB WIP 2
2025-12-27 01:02:47 +01:00
MAIN.~(24).PcbDoc.Zip
PCB WIP 2
2025-12-27 01:02:47 +01:00
MAIN.~(25).PcbDoc.Zip
PCB WIP 2
2025-12-27 01:02:47 +01:00
MAIN.~(26).PcbDoc.Zip
PCB WIP 2
2025-12-27 01:02:47 +01:00
MAIN.~(27).PcbDoc.Zip
PCB WIP 2
2025-12-27 01:02:47 +01:00
MAIN.~(28).PcbDoc.Zip
PCB WIP 2
2025-12-27 01:02:47 +01:00
MAIN.~(29).PcbDoc.Zip
PCB WIP 2
2025-12-27 01:02:47 +01:00
MAIN.~(30).PcbDoc.Zip
PCB WIP 2
2025-12-27 01:02:47 +01:00
MAIN.~(31).PcbDoc.Zip
PCB WIP 2
2025-12-27 01:02:47 +01:00
MAIN.~(32).PcbDoc.Zip
PCB WIP 2
2025-12-27 01:02:47 +01:00
MAIN.~(33).PcbDoc.Zip
PCB WIP 2
2025-12-27 01:02:47 +01:00
MAIN.~(34).PcbDoc.Zip
PCB WIP 2
2025-12-27 01:02:47 +01:00
MAIN.~(35).PcbDoc.Zip
PCB done
2025-12-28 22:38:23 +01:00
MAIN.~(36).PcbDoc.Zip
PCB done
2025-12-28 22:38:23 +01:00
MAIN.~(37).PcbDoc.Zip
PCB done
2025-12-28 22:38:23 +01:00
MAIN.~(38).PcbDoc.Zip
PCB done
2025-12-28 22:38:23 +01:00
MAIN.~(39).PcbDoc.Zip
PCB done
2025-12-28 22:38:23 +01:00
MainSys.~(1).PrjPcb.Zip
Created project for PCB
2025-12-10 07:38:23 +01:00
MainSys.~(4).PrjPcb.Zip
Edits DA Lib and General Schematics
2025-12-11 06:59:11 +01:00
MainSys.~(5).PrjPcb.Zip
Main schematic update
2025-12-11 20:43:15 +01:00
MainSys.~(6).PrjPcb.Zip
Main schematic update
2025-12-11 20:43:15 +01:00
MainSys.~(7).PrjPcb.Zip
Main schematic update
2025-12-11 20:43:15 +01:00
MainSys.~(8).PrjPcb.Zip
Main schematic update
2025-12-11 20:43:15 +01:00
MainSys.~(9).PrjPcb.Zip
Main schematic update
2025-12-11 20:43:15 +01:00
MainSys.~(33).PrjPcb.Zip
Main schematic progress; checked VCA -> Voice Mixer compatibilty; DA Lib Update to V3.2
2025-12-14 16:41:19 +01:00
MainSys.~(34).PrjPcb.Zip
PCB main schematic progress
2025-12-18 16:28:24 +01:00
MainSys.~(35).PrjPcb.Zip
PCB main schematic progress
2025-12-18 16:28:24 +01:00
MainSys.~(36).PrjPcb.Zip
Started PCB Design
2025-12-24 23:04:43 +01:00
MainSys.~(37).PrjPcb.Zip
Started PCB Design
2025-12-24 23:04:43 +01:00
MainSys.~(38).PrjPcb.Zip
Started PCB Design
2025-12-24 23:04:43 +01:00
MainSys.~(39).PrjPcb.Zip
Started PCB Design
2025-12-24 23:04:43 +01:00
MainSys.~(40).PrjPcb.Zip
Started PCB Design
2025-12-24 23:04:43 +01:00
MainSys.~(41).PrjPcb.Zip
Started PCB Design
2025-12-24 23:04:43 +01:00
MainSys.~(42).PrjPcb.Zip
Started PCB Design
2025-12-24 23:04:43 +01:00
MainSys.~(43).PrjPcb.Zip
Started PCB Design
2025-12-24 23:04:43 +01:00
MainSys.~(44).PrjPcb.Zip
Started PCB Design
2025-12-24 23:04:43 +01:00
MainSys.~(45).PrjPcb.Zip
Started PCB Design
2025-12-24 23:04:43 +01:00
MainSys.~(46).PrjPcb.Zip
Started PCB Design
2025-12-24 23:04:43 +01:00
MainSys.~(47).PrjPcb.Zip
Started PCB Design
2025-12-24 23:04:43 +01:00
MainSys.~(48).PrjPcb.Zip
PCB WIP
2025-12-26 00:42:46 +01:00
MainSys.~(49).PrjPcb.Zip
PCB WIP 2
2025-12-27 01:02:47 +01:00
MainSys.~(50).PrjPcb.Zip
PCB WIP 2
2025-12-27 01:02:47 +01:00
MainSys.~(51).PrjPcb.Zip
PCB WIP 2
2025-12-27 01:02:47 +01:00
MainSys.~(52).PrjPcb.Zip
PCB WIP 2
2025-12-27 01:02:47 +01:00
MainSys.~(53).PrjPcb.Zip
PCB WIP 2
2025-12-27 01:02:47 +01:00
MainSys.~(54).PrjPcb.Zip
PCB WIP 2
2025-12-27 01:02:47 +01:00
MainSys.~(55).PrjPcb.Zip
PCB WIP 2
2025-12-27 01:02:47 +01:00
MainSys.~(56).PrjPcb.Zip
PCB done
2025-12-28 22:38:23 +01:00
MainSys.~(57).PrjPcb.Zip
PCB done
2025-12-28 22:38:23 +01:00
MainSys.~(58).PrjPcb.Zip
PCB done
2025-12-28 22:38:23 +01:00
MainSys.~(59).PrjPcb.Zip
PCB done
2025-12-28 22:38:23 +01:00
MCU.~(1).SchDoc.Zip
Edits DA Lib and General Schematics
2025-12-11 06:59:11 +01:00
MCU.~(2).SchDoc.Zip
Edits DA Lib and General Schematics
2025-12-11 06:59:11 +01:00
MCU.~(3).SchDoc.Zip
Edits DA Lib and General Schematics
2025-12-11 06:59:11 +01:00
MCU.~(4).SchDoc.Zip
Edits DA Lib and General Schematics
2025-12-11 06:59:11 +01:00
MCU.~(5).SchDoc.Zip
Edits DA Lib and General Schematics
2025-12-11 06:59:11 +01:00
MCU.~(6).SchDoc.Zip
Edits DA Lib and General Schematics
2025-12-11 06:59:11 +01:00
MCU.~(7).SchDoc.Zip
Edits DA Lib and General Schematics
2025-12-11 06:59:11 +01:00
MCU.~(8).SchDoc.Zip
Corretion on project_sim
2025-12-11 15:02:34 +01:00
MCU.~(9).SchDoc.Zip
Corretion on project_sim
2025-12-11 15:02:34 +01:00
MCU.~(14).SchDoc.Zip
Corretion on project_sim
2025-12-11 15:02:34 +01:00
MCU.~(15).SchDoc.Zip
Corretion on project_sim
2025-12-11 15:02:34 +01:00
MCU.~(16).SchDoc.Zip
Corretion on project_sim
2025-12-11 15:02:34 +01:00
MCU.~(17).SchDoc.Zip
Corretion on project_sim
2025-12-11 15:02:34 +01:00
MCU.~(18).SchDoc.Zip
Corretion on project_sim
2025-12-11 15:02:34 +01:00
MCU.~(19).SchDoc.Zip
Main schematic update
2025-12-11 20:43:15 +01:00
MCU.~(20).SchDoc.Zip
Main schematic update
2025-12-11 20:43:15 +01:00
MCU.~(21).SchDoc.Zip
Main schematic update
2025-12-11 20:43:15 +01:00
MCU.~(22).SchDoc.Zip
Main schematic update
2025-12-11 20:43:15 +01:00
MCU.~(23).SchDoc.Zip
Main schematic update
2025-12-11 20:43:15 +01:00
MCU.~(24).SchDoc.Zip
Main schematic update
2025-12-11 20:43:15 +01:00
MCU.~(25).SchDoc.Zip
Main schematic update
2025-12-11 20:43:15 +01:00
MCU.~(26).SchDoc.Zip
Main schematic update
2025-12-11 20:43:15 +01:00
MCU.~(27).SchDoc.Zip
Main schematic update
2025-12-11 20:43:15 +01:00
MCU.~(28).SchDoc.Zip
Main schematic update
2025-12-11 20:43:15 +01:00
MCU.~(29).SchDoc.Zip
Main schematic update
2025-12-11 20:43:15 +01:00
MCU.~(30).SchDoc.Zip
Main schematic update
2025-12-11 20:43:15 +01:00
MCU.~(31).SchDoc.Zip
Main schematic update
2025-12-11 20:43:15 +01:00
MCU.~(32).SchDoc.Zip
Main schematic update
2025-12-11 20:43:15 +01:00
MCU.~(33).SchDoc.Zip
Main schematic update
2025-12-11 20:43:15 +01:00
MCU.~(34).SchDoc.Zip
Main schematic update
2025-12-11 20:43:15 +01:00
MCU.~(35).SchDoc.Zip
Main schematic update
2025-12-11 20:43:15 +01:00
MCU.~(36).SchDoc.Zip
Main schematic update
2025-12-11 20:43:15 +01:00
MCU.~(37).SchDoc.Zip
Main schematic update
2025-12-11 20:43:15 +01:00
MCU.~(38).SchDoc.Zip
Harness for SC1 and SC2 added
2025-12-11 22:58:54 +01:00
MCU.~(39).SchDoc.Zip
Further additions general schematics
2025-12-13 11:36:54 +01:00
MCU.~(40).SchDoc.Zip
Further additions general schematics
2025-12-13 11:36:54 +01:00
MCU.~(41).SchDoc.Zip
Further additions general schematics
2025-12-13 11:36:54 +01:00
MCU.~(42).SchDoc.Zip
Further additions general schematics
2025-12-13 11:36:54 +01:00
MCU.~(43).SchDoc.Zip
Further additions general schematics
2025-12-13 11:36:54 +01:00
MCU.~(44).SchDoc.Zip
Further additions general schematics
2025-12-13 11:36:54 +01:00
MCU.~(45).SchDoc.Zip
PCB main schematic progress
2025-12-18 16:28:24 +01:00
MCU.~(46).SchDoc.Zip
PCB main schematic progress
2025-12-18 16:28:24 +01:00
MCU.~(47).SchDoc.Zip
PCB main schematic progress
2025-12-18 16:28:24 +01:00
MCU.~(48).SchDoc.Zip
PCB main schematic progress
2025-12-18 16:28:24 +01:00
MCU.~(49).SchDoc.Zip
PCB main schematic progress
2025-12-18 16:28:24 +01:00
MCU.~(50).SchDoc.Zip
Started PCB Design
2025-12-24 23:04:43 +01:00
MCU.~(51).SchDoc.Zip
PCB WIP 2
2025-12-27 01:02:47 +01:00
MCU.~(52).SchDoc.Zip
PCB WIP 2
2025-12-27 01:02:47 +01:00
MCU.~(53).SchDoc.Zip
PCB WIP 2
2025-12-27 01:02:47 +01:00
OS.~(1).SchDoc.Zip
Further additions general schematics
2025-12-13 11:36:54 +01:00
OS.~(9).SchDoc.Zip
Started PCB Design
2025-12-24 23:04:43 +01:00
OS.~(10).SchDoc.Zip
Started PCB Design
2025-12-24 23:04:43 +01:00
OS.~(11).SchDoc.Zip
Started PCB Design
2025-12-24 23:04:43 +01:00
OS.~(12).SchDoc.Zip
PCB WIP 2
2025-12-27 01:02:47 +01:00
OS.~(13).SchDoc.Zip
PCB WIP 2
2025-12-27 01:02:47 +01:00
OS.~(14).SchDoc.Zip
PCB WIP 2
2025-12-27 01:02:47 +01:00
OS.~(15).SchDoc.Zip
PCB WIP 2
2025-12-27 01:02:47 +01:00
OS.~(16).SchDoc.Zip
PCB WIP 2
2025-12-27 01:02:47 +01:00
OS.~(17).SchDoc.Zip
PCB WIP 2
2025-12-27 01:02:47 +01:00
PCB1.~(1).PcbDoc.Zip
Further additions general schematics
2025-12-13 11:36:54 +01:00
PCB1.~(2).#(Deleted).PcbDoc.Zip
Further additions general schematics
2025-12-13 11:36:54 +01:00
PCB_GERBER.~(1).#(Deleted).Cam.Zip
PCB done
2025-12-28 22:38:23 +01:00
PCB_NCDRILL1.~(1).#(Deleted).Cam.Zip
PCB done
2025-12-28 22:38:23 +01:00
PM.~(1).SchDoc.Zip
Created project for PCB
2025-12-10 07:38:23 +01:00
PM.~(2).SchDoc.Zip
Created project for PCB
2025-12-10 07:38:23 +01:00
PM.~(3).SchDoc.Zip
Created project for PCB
2025-12-10 07:38:23 +01:00
PM.~(4).SchDoc.Zip
Created project for PCB
2025-12-10 07:38:23 +01:00
PM.~(5).SchDoc.Zip
Created project for PCB
2025-12-10 07:38:23 +01:00
PM.~(6).SchDoc.Zip
Edits DA Lib and General Schematics
2025-12-11 06:59:11 +01:00
PM.~(7).SchDoc.Zip
Edits DA Lib and General Schematics
2025-12-11 06:59:11 +01:00
PM.~(8).SchDoc.Zip
Edits DA Lib and General Schematics
2025-12-11 06:59:11 +01:00
PM.~(9).SchDoc.Zip
Edits DA Lib and General Schematics
2025-12-11 06:59:11 +01:00
PM.~(14).SchDoc.Zip
Further additions general schematics
2025-12-13 11:36:54 +01:00
PM.~(15).SchDoc.Zip
Further additions general schematics
2025-12-13 11:36:54 +01:00
PM.~(16).SchDoc.Zip
Further additions general schematics
2025-12-13 11:36:54 +01:00
PM.~(17).SchDoc.Zip
Further additions general schematics
2025-12-13 11:36:54 +01:00
PM.~(18).SchDoc.Zip
Started PCB Design
2025-12-24 23:04:43 +01:00
PM.~(19).SchDoc.Zip
PCB WIP 2
2025-12-27 01:02:47 +01:00
PM.~(20).SchDoc.Zip
PCB WIP 2
2025-12-27 01:02:47 +01:00
PM.~(21).SchDoc.Zip
PCB WIP 2
2025-12-27 01:02:47 +01:00
SC.~(1).SchDoc.Zip
Main schematic update
2025-12-11 20:43:15 +01:00
SC.~(7).SchDoc.Zip
Started PCB Design
2025-12-24 23:04:43 +01:00
SC.~(8).SchDoc.Zip
Started PCB Design
2025-12-24 23:04:43 +01:00
SC.~(9).SchDoc.Zip
Started PCB Design
2025-12-24 23:04:43 +01:00
SC.~(10).SchDoc.Zip
Started PCB Design
2025-12-24 23:04:43 +01:00
SC.~(11).SchDoc.Zip
Started PCB Design
2025-12-24 23:04:43 +01:00
SC.~(12).SchDoc.Zip
Started PCB Design
2025-12-24 23:04:43 +01:00
TOP.~(1).SchDoc.Zip
Created project for PCB
2025-12-10 07:38:23 +01:00
TOP.~(2).SchDoc.Zip
Created project for PCB
2025-12-10 07:38:23 +01:00
TOP.~(3).SchDoc.Zip
Created project for PCB
2025-12-10 07:38:23 +01:00
TOP.~(4).SchDoc.Zip
Created project for PCB
2025-12-10 07:38:23 +01:00
TOP.~(5).SchDoc.Zip
Created project for PCB
2025-12-10 07:38:23 +01:00
TOP.~(6).SchDoc.Zip
Created project for PCB
2025-12-10 07:38:23 +01:00
TOP.~(7).SchDoc.Zip
Created project for PCB
2025-12-10 07:38:23 +01:00
TOP.~(8).SchDoc.Zip
Created project for PCB
2025-12-10 07:38:23 +01:00
TOP.~(9).SchDoc.Zip
Created project for PCB
2025-12-10 07:38:23 +01:00
TOP.~(20).SchDoc.Zip
Edits DA Lib and General Schematics
2025-12-11 06:59:11 +01:00
TOP.~(21).SchDoc.Zip
Main schematic update
2025-12-11 20:43:15 +01:00
TOP.~(22).SchDoc.Zip
Main schematic update
2025-12-11 20:43:15 +01:00
TOP.~(23).SchDoc.Zip
Main schematic update
2025-12-11 20:43:15 +01:00
TOP.~(24).SchDoc.Zip
Main schematic update
2025-12-11 20:43:15 +01:00
TOP.~(25).SchDoc.Zip
Main schematic update
2025-12-11 20:43:15 +01:00
TOP.~(26).SchDoc.Zip
Main schematic update
2025-12-11 20:43:15 +01:00
TOP.~(27).SchDoc.Zip
Main schematic update
2025-12-11 20:43:15 +01:00
TOP.~(28).SchDoc.Zip
Main schematic update
2025-12-11 20:43:15 +01:00
TOP.~(29).SchDoc.Zip
Harness for SC1 and SC2 added
2025-12-11 22:58:54 +01:00
TOP.~(30).SchDoc.Zip
Harness for SC1 and SC2 added
2025-12-11 22:58:54 +01:00
TOP.~(31).SchDoc.Zip
Harness for SC1 and SC2 added
2025-12-11 22:58:54 +01:00
TOP.~(32).SchDoc.Zip
Harness for SC1 and SC2 added
2025-12-11 22:58:54 +01:00
TOP.~(33).SchDoc.Zip
Harness for SC1 and SC2 added
2025-12-11 22:58:54 +01:00
TOP.~(34).SchDoc.Zip
Harness for SC1 and SC2 added
2025-12-11 22:58:54 +01:00
TOP.~(35).SchDoc.Zip
Harness for SC1 and SC2 added
2025-12-11 22:58:54 +01:00
TOP.~(36).SchDoc.Zip
Harness for SC1 and SC2 added
2025-12-11 22:58:54 +01:00
TOP.~(37).SchDoc.Zip
Harness for SC1 and SC2 added
2025-12-11 22:58:54 +01:00
TOP.~(38).SchDoc.Zip
Further additions general schematics
2025-12-13 11:36:54 +01:00
TOP.~(39).SchDoc.Zip
Further additions general schematics
2025-12-13 11:36:54 +01:00
TOP.~(40).SchDoc.Zip
Further additions general schematics
2025-12-13 11:36:54 +01:00
TOP.~(41).SchDoc.Zip
Further additions general schematics
2025-12-13 11:36:54 +01:00
TOP.~(42).SchDoc.Zip
Further additions general schematics
2025-12-13 11:36:54 +01:00
TOP.~(43).SchDoc.Zip
Further additions general schematics
2025-12-13 11:36:54 +01:00
TOP.~(44).SchDoc.Zip
Further additions general schematics
2025-12-13 11:36:54 +01:00
TOP.~(45).SchDoc.Zip
Further additions general schematics
2025-12-13 11:36:54 +01:00
TOP.~(46).SchDoc.Zip
Further additions general schematics
2025-12-13 11:36:54 +01:00
TOP.~(47).SchDoc.Zip
Further additions general schematics
2025-12-13 11:36:54 +01:00
TOP.~(48).SchDoc.Zip
Further additions general schematics
2025-12-13 11:36:54 +01:00
TOP.~(49).SchDoc.Zip
Further additions general schematics
2025-12-13 11:36:54 +01:00
TOP.~(50).SchDoc.Zip
Further additions general schematics
2025-12-13 11:36:54 +01:00
TOP.~(51).SchDoc.Zip
Further additions general schematics
2025-12-13 11:36:54 +01:00
TOP.~(52).SchDoc.Zip
Further additions general schematics
2025-12-13 11:36:54 +01:00
TOP.~(53).SchDoc.Zip
Further additions general schematics
2025-12-13 11:36:54 +01:00
TOP.~(54).SchDoc.Zip
Main schematic progress; checked VCA -> Voice Mixer compatibilty; DA Lib Update to V3.2
2025-12-14 16:41:19 +01:00
TOP.~(55).SchDoc.Zip
PCB main schematic progress
2025-12-18 16:28:24 +01:00
TOP.~(56).SchDoc.Zip
Started PCB Design
2025-12-24 23:04:43 +01:00
TOP.~(57).SchDoc.Zip
Started PCB Design
2025-12-24 23:04:43 +01:00
TOP.~(58).SchDoc.Zip
Started PCB Design
2025-12-24 23:04:43 +01:00
TOP.~(59).SchDoc.Zip
Started PCB Design
2025-12-24 23:04:43 +01:00
TOP.~(60).SchDoc.Zip
Started PCB Design
2025-12-24 23:04:43 +01:00
TOP.~(61).SchDoc.Zip
PCB WIP 2
2025-12-27 01:02:47 +01:00
TOP.~(62).SchDoc.Zip
PCB WIP 2
2025-12-27 01:02:47 +01:00
TOP.~(63).SchDoc.Zip
PCB WIP 2
2025-12-27 01:02:47 +01:00
TOP.~(64).SchDoc.Zip
PCB WIP 2
2025-12-27 01:02:47 +01:00
VCA.~(1).SchDoc.Zip
Harness for SC1 and SC2 added
2025-12-11 22:58:54 +01:00
VCA.~(2).SchDoc.Zip
Harness for SC1 and SC2 added
2025-12-11 22:58:54 +01:00
VCA.~(3).SchDoc.Zip
Harness for SC1 and SC2 added
2025-12-11 22:58:54 +01:00
VCA.~(4).SchDoc.Zip
Further additions general schematics
2025-12-13 11:36:54 +01:00
VCA.~(5).SchDoc.Zip
Further additions general schematics
2025-12-13 11:36:54 +01:00
VCA.~(6).SchDoc.Zip
Further additions general schematics
2025-12-13 11:36:54 +01:00
VCA.~(7).SchDoc.Zip
Further additions general schematics
2025-12-13 11:36:54 +01:00
VCA.~(8).SchDoc.Zip
Main schematic progress; checked VCA -> Voice Mixer compatibilty; DA Lib Update to V3.2
2025-12-14 16:41:19 +01:00
VCA.~(9).SchDoc.Zip
Main schematic progress; checked VCA -> Voice Mixer compatibilty; DA Lib Update to V3.2
2025-12-14 16:41:19 +01:00
VCA.~(11).SchDoc.Zip
Main schematic progress; checked VCA -> Voice Mixer compatibilty; DA Lib Update to V3.2
2025-12-14 16:41:19 +01:00
VCA.~(12).SchDoc.Zip
Main schematic progress; checked VCA -> Voice Mixer compatibilty; DA Lib Update to V3.2
2025-12-14 16:41:19 +01:00
VCA.~(13).SchDoc.Zip
PCB main schematic progress
2025-12-18 16:28:24 +01:00
VCA.~(14).SchDoc.Zip
PCB main schematic progress
2025-12-18 16:28:24 +01:00
VCA.~(15).SchDoc.Zip
PCB main schematic progress
2025-12-18 16:28:24 +01:00
VCA.~(16).SchDoc.Zip
PCB main schematic progress
2025-12-18 16:28:24 +01:00
VCA.~(17).SchDoc.Zip
PCB main schematic progress
2025-12-18 16:28:24 +01:00
VCA.~(18).SchDoc.Zip
PCB main schematic progress
2025-12-18 16:28:24 +01:00
VCA.~(19).SchDoc.Zip
PCB main schematic progress
2025-12-18 16:28:24 +01:00
VCA.~(20).SchDoc.Zip
PCB main schematic progress
2025-12-18 16:28:24 +01:00
VCA.~(21).#(Deleted).SchDoc.Zip
Started PCB Design
2025-12-24 23:04:43 +01:00
VCF_A.~(1).SchDoc.Zip
Started PCB Design
2025-12-24 23:04:43 +01:00
VCF_A.~(2).SchDoc.Zip
Started PCB Design
2025-12-24 23:04:43 +01:00
VCF_A.~(3).SchDoc.Zip
Started PCB Design
2025-12-24 23:04:43 +01:00
VCF_A.~(4).SchDoc.Zip
Started PCB Design
2025-12-24 23:04:43 +01:00
VCF_A.~(5).SchDoc.Zip
Started PCB Design
2025-12-24 23:04:43 +01:00
VCF_A.~(6).SchDoc.Zip
Started PCB Design
2025-12-24 23:04:43 +01:00
VCF_A.~(7).SchDoc.Zip
Started PCB Design
2025-12-24 23:04:43 +01:00
VCF_A.~(8).SchDoc.Zip
Started PCB Design
2025-12-24 23:04:43 +01:00
VCF_A.~(9).SchDoc.Zip
Started PCB Design
2025-12-24 23:04:43 +01:00
VCF_A.~(10).SchDoc.Zip
Started PCB Design
2025-12-24 23:04:43 +01:00
VCF_A.~(11).SchDoc.Zip
Started PCB Design
2025-12-24 23:04:43 +01:00
VCF_A.~(12).SchDoc.Zip
Started PCB Design
2025-12-24 23:04:43 +01:00
VCF_A.~(13).SchDoc.Zip
Started PCB Design
2025-12-24 23:04:43 +01:00
VCF_A.~(14).SchDoc.Zip
Started PCB Design
2025-12-24 23:04:43 +01:00
VCF_A.~(15).SchDoc.Zip
PCB WIP 2
2025-12-27 01:02:47 +01:00
VCF_A.~(16).SchDoc.Zip
PCB WIP 2
2025-12-27 01:02:47 +01:00
VCF_A.~(17).SchDoc.Zip
PCB WIP 2
2025-12-27 01:02:47 +01:00
VCF.~(1).SchDoc.Zip
Harness for SC1 and SC2 added
2025-12-11 22:58:54 +01:00
VCF.~(2).SchDoc.Zip
Harness for SC1 and SC2 added
2025-12-11 22:58:54 +01:00
VCF.~(3).SchDoc.Zip
Further additions general schematics
2025-12-13 11:36:54 +01:00
VCF.~(4).SchDoc.Zip
Further additions general schematics
2025-12-13 11:36:54 +01:00
VCF.~(5).SchDoc.Zip
Further additions general schematics
2025-12-13 11:36:54 +01:00
VCF.~(6).SchDoc.Zip
Further additions general schematics
2025-12-13 11:36:54 +01:00
VCF.~(7).SchDoc.Zip
Main schematic progress; checked VCA -> Voice Mixer compatibilty; DA Lib Update to V3.2
2025-12-14 16:41:19 +01:00
VCF.~(8).SchDoc.Zip
Main schematic progress; checked VCA -> Voice Mixer compatibilty; DA Lib Update to V3.2
2025-12-14 16:41:19 +01:00
VCO.~(1).SchDoc.Zip
Main schematic update
2025-12-11 20:43:15 +01:00
VCO.~(2).SchDoc.Zip
Harness for SC1 and SC2 added
2025-12-11 22:58:54 +01:00
VCO.~(3).SchDoc.Zip
Harness for SC1 and SC2 added
2025-12-11 22:58:54 +01:00
VCO.~(4).SchDoc.Zip
Harness for SC1 and SC2 added
2025-12-11 22:58:54 +01:00
VCO.~(5).SchDoc.Zip
Further additions general schematics
2025-12-13 11:36:54 +01:00
VCO.~(6).SchDoc.Zip
Further additions general schematics
2025-12-13 11:36:54 +01:00
VCO.~(7).SchDoc.Zip
Further additions general schematics
2025-12-13 11:36:54 +01:00
VCO.~(8).SchDoc.Zip
Further additions general schematics
2025-12-13 11:36:54 +01:00
VCO.~(9).SchDoc.Zip
Further additions general schematics
2025-12-13 11:36:54 +01:00
VCO.~(19).SchDoc.Zip
Further additions general schematics
2025-12-13 11:36:54 +01:00
VCO.~(20).SchDoc.Zip
Further additions general schematics
2025-12-13 11:36:54 +01:00
VCO.~(21).SchDoc.Zip
Further additions general schematics
2025-12-13 11:36:54 +01:00
VCO.~(22).SchDoc.Zip
Further additions general schematics
2025-12-13 11:36:54 +01:00
VCO.~(23).SchDoc.Zip
Further additions general schematics
2025-12-13 11:36:54 +01:00
VCO.~(24).SchDoc.Zip
Further additions general schematics
2025-12-13 11:36:54 +01:00
VCO.~(25).SchDoc.Zip
Further additions general schematics
2025-12-13 11:36:54 +01:00
VCO.~(26).SchDoc.Zip
Further additions general schematics
2025-12-13 11:36:54 +01:00
VCO.~(27).SchDoc.Zip
Further additions general schematics
2025-12-13 11:36:54 +01:00
VCO.~(28).SchDoc.Zip
Further additions general schematics
2025-12-13 11:36:54 +01:00
VCO.~(29).SchDoc.Zip
Further additions general schematics
2025-12-13 11:36:54 +01:00
VCO.~(30).SchDoc.Zip
Further additions general schematics
2025-12-13 11:36:54 +01:00
VCO.~(31).SchDoc.Zip
Further additions general schematics
2025-12-13 11:36:54 +01:00
VCO.~(32).SchDoc.Zip
Further additions general schematics
2025-12-13 11:36:54 +01:00
VCO.~(33).SchDoc.Zip
Further additions general schematics
2025-12-13 11:36:54 +01:00
VCO.~(34).SchDoc.Zip
Further additions general schematics
2025-12-13 11:36:54 +01:00
VCO.~(35).SchDoc.Zip
Further additions general schematics
2025-12-13 11:36:54 +01:00
VCO.~(36).SchDoc.Zip
Further additions general schematics
2025-12-13 11:36:54 +01:00
VCO.~(37).SchDoc.Zip
Further additions general schematics
2025-12-13 11:36:54 +01:00
VCO.~(38).SchDoc.Zip
Further additions general schematics
2025-12-13 11:36:54 +01:00
VCO.~(39).SchDoc.Zip
Main schematic progress; checked VCA -> Voice Mixer compatibilty; DA Lib Update to V3.2
2025-12-14 16:41:19 +01:00
VCO.~(40).SchDoc.Zip
PCB main schematic progress
2025-12-18 16:28:24 +01:00
VCO.~(41).SchDoc.Zip
PCB main schematic progress
2025-12-18 16:28:24 +01:00
VCO.~(42).SchDoc.Zip
PCB main schematic progress
2025-12-18 16:28:24 +01:00
VCO.~(43).SchDoc.Zip
Started PCB Design
2025-12-24 23:04:43 +01:00
VCO.~(44).SchDoc.Zip
Started PCB Design
2025-12-24 23:04:43 +01:00
VCO.~(45).SchDoc.Zip
PCB WIP
2025-12-26 00:42:46 +01:00
VCO.~(46).SchDoc.Zip
PCB WIP
2025-12-26 00:42:46 +01:00
VCO.~(47).SchDoc.Zip
PCB WIP
2025-12-26 00:42:46 +01:00
VCO.~(48).SchDoc.Zip
PCB WIP 2
2025-12-27 01:02:47 +01:00
VCO.~(49).SchDoc.Zip
PCB WIP 2
2025-12-27 01:02:47 +01:00
VCO.~(50).SchDoc.Zip
PCB WIP 2
2025-12-27 01:02:47 +01:00
VCO.~(51).SchDoc.Zip
PCB WIP 2
2025-12-27 01:02:47 +01:00