17 Commits

Author SHA1 Message Date
Wendelin Waldhart
256acf7356 Merge branch 'main' of https://github.com/erik-toth/audio-synth 2025-12-22 13:11:56 +01:00
Wendelin Waldhart
9798c31663 VCF added HP, small circuit changes, changed controll current 2025-12-22 13:07:24 +01:00
d294c74a4b Update TO-DO list and version history in README 2025-12-18 16:34:32 +01:00
1df705d7e2 PCB main schematic progress
TOP done; MCU done; CV_GEN done; VCO done; PM done; VCA done; OS done; waiting for VCF; EXT waiting until VCF done
2025-12-18 16:28:24 +01:00
2a51182080 Main schematic progress; checked VCA -> Voice Mixer compatibilty; DA Lib Update to V3.2
VCA-Voice Mixer checked if there might be a problem because of the offset, checked out to be ok after some minor fixes
2025-12-14 16:41:19 +01:00
8999384170 Further additions general schematics
MCU mostly done; VCO mostly done; PM mostly done; started OS; going to begin VCA; waiting for VCF
2025-12-13 11:36:54 +01:00
Wendelin Waldhart
d7025a91f9 Added Octave +2 Shift, Changed Designators for 8-Shift, Normalized Restistance Values for PWM, Small changes changes uC-Compensation 2025-12-12 14:52:32 +01:00
19db4a9944 Harness for SC1 and SC2 added 2025-12-11 22:58:54 +01:00
ab940cbafc Main schematic update
MCU mostly finished; PM mostly finished, VCM not done yet; Status LED not done
2025-12-11 20:43:15 +01:00
3091411d4d Corretion on project_sim 2025-12-11 15:02:34 +01:00
Wendelin Waldhart
43ef4b4651 Merge branch 'main' of https://github.com/erik-toth/audio-synth 2025-12-11 14:04:04 +01:00
4c50a877b8 Edits DA Lib and General Schematics
Powermanagement VCM inn't done yet; in Process of creating the MCU schematic
2025-12-11 06:59:11 +01:00
fe564a01f9 Created project for PCB
Initial configuartion
2025-12-10 07:38:23 +01:00
59179ad669 Small library changes
in the next days there will be again a version update
2025-12-09 22:30:21 +01:00
c8e13d09d1 TRI2SAW Labor
Analog Discovery 3 Aufbau Erik Tóth
2025-12-09 16:38:58 +01:00
f873af11e4 Added Transistor Matched Pair PNP and Push-Pull for VCM
affected Project: ETOTH-TRI-SQR_VCO_SS
2025-12-09 15:14:57 +01:00
Wendelin Waldhart
36a04e7ed5 SAW/PWM-Test, Thermal Compensation Sim 2025-12-09 13:19:52 +01:00
792 changed files with 14786 additions and 25419 deletions

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@@ -1,5 +1,5 @@
ETOTH-Amp_LM386
*SPICE Netlist generated by Advanced Sim server on 08.12.2025 13:48:55
*SPICE Netlist generated by Advanced Sim server on 17.12.2025 16:45:18
.options MixedSimGenerated
*Schematic Netlist:
@@ -11,18 +11,19 @@ LL_Speaker 0 NetL_Speaker_2 0.1mH
RR_POTA 0 NetR_POT_2 {10k * {POS}}
RR_POTB NetR_POT_2 IN_FILT {10k - (10k * {POS})}
RR_Speaker NetL_Speaker_2 OUT 4R
RR_static1 NetIC1_3 NetR_POT_2 100k
RR_static1 NetIC1_3 NetR_POT_2 75k
RR_static2 0 NetIC1_3 10k
VU_q VAP 0 10V
VUin IN 0 DC 0 SIN(5 2 220 0 0 0) AC 1 0
.PLOT AC {MAG(v(OUT))} =PLOT(1) =AXIS(1) =NAME(A_Speaker)
.PLOT TRAN {v(IN)} =PLOT(1) =AXIS(1) =NAME(U_IN) =UNITS(V) =RGB(0, 0, 255)
.PLOT TRAN {v(OUT)} =PLOT(2) =AXIS(1) =NAME(U_OUT) =UNITS(V) =RGB(255, 153, 0)
.OPTIONS METHOD=GEAR MAXORD=2
*Selected Circuit Analyses:
.AC DEC 50 22 22000
.TRAN 90.91u 22.73m 0 90.91u
.CONTROL
SWEEP C_DCBLOCK_OUT LIST 100u 150u 220u 330u 470u 680u
SWEEP POS LIST 1
.ENDC
*Global Parameters:

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@@ -7,4 +7,4 @@ From : Project [ETOTH-Amp_LM386.PrjPcb]
Files Generated : 1
Documents Printed : 0
Finished Output Generation At 13:33:33 On 08.12.2025
Finished Output Generation At 16:43:39 On 17.12.2025

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